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while the interface may look like a common graphic interface, there are a number of deeper features that help get to the heart of the design. fpga problems are not always as simple as they first appear, with layers of communication and timing issues between blocks or between the fpga and the rest of the ic, sometimes a network of defects can result in unwanted behavior.
for example, a 10-stage pipeline in a design would have a total of 20 signal paths, 20 control-related wires, and 20 power supply wires. if the oscillator timing is perfectly designed, everything functions perfectly, however, a typical asic might have hundreds of other design elements that could cause any one signal to propagate beyond its desired timing window. this could cause an edge to appear at a different stage than expected, causing the circuit to malfunction.
using a friendly database of allowed pairs, such as a hard match, soft match, and soft fail information, the system allows for a flexible yet comprehensive modification engine that can handle different timing requirements throughout the design, from the trivial case of a 10-cycle latency requirement, to the tens of nanoseconds for a data-driven design.